1. Field of the Invention
The present invention relates to a circuit and a method for baseline wandering compensation. More particularly, the present invention relates to a circuit and a method for baseline wandering compensation that uses a baseline corrector to adjust a baseline wandering compensation.
2. Description of Related Art
When data are transmitted in channels, low-frequency signals are often generated due to the imbalance between positive and negative signals. Moreover, as the currently-used transformer is not perfect, it cannot only filter out DC signals, signals at lower frequencies are distorted, and thus a DC bias occurs. Thus, the linearity and the signal-to-noise ratio (SNR) are reduced, or in another aspect, input signals exceed the allowed swing range of an analog-to-digital converter (ADC), which causes ADC saturation. The above phenomenon is defined as baseline wandering.
In general, two methods are mainly used for the baseline wandering compensation. FIG. 1 shows a first baseline wandering compensation method. Referring to FIG. 1, this method mainly uses a feedback control to adjust a DC bias of a front end signal BX that enters an ADC 102. The circuit of FIG. 1 includes an analog signal processor S110 and a digital signal processor S120. The analog signal BX is converted to a digital signal DX by the ADC 102, and then, an equalizer 103 eliminates the channel effect of the digital signal DX, and outputs a signal EX to a slicer 104. The digital signal processor S120 is mainly used to utilize the slicer 104 to recover the output signal EX of the equalizer 103 to original state values (e.g., MLT-3 encoded −1, 0, and 1) when the output signal EX was sent out from a sending terminal. A baseline corrector 105 calculates an error SX before and after the recovery, i.e., the error before and after the signal EX passes through the slicer 104, and outputs the error SX as a compensation CX to a digital-to-analog converter (DAC) 106. The DAC 106 converts the compensation CX from a digital signal to an analog signal AX, and a baseline compensator 101 uses the analog compensation AX to adjust a DC bias of an input signal RX.
The method of FIG. 1 has an advantage that, as the input signal RX is compensated before entering the ADC 102, and thus the input saturation of the ADC 102 is avoided. However, the disadvantage of the method of FIG. 1 lies in that, the precision of the compensation CX is limited by number of bits of the DAC 106 and the ADC 102, so precise compensation cannot be achieved if the baseline wandering is relatively small.
FIG. 2 shows a second baseline wandering compensation method. Referring to FIG. 2, the circuit of FIG. 2 includes an analog signal processor S210 and a digital signal processor S220. This method mainly aims at adjusting a determining level of a slicer 203 at the digital signal processor S220, so as to compensate the baseline wandering precisely and timely. In the digital signal processor S220, an equalizer 202 receives a digitalized signal DY output from an ADC 201, and then eliminates the channel effect of the signal DY and outputs a signal EY Then, a feedback circuit is disposed, in which the slicer 203 adjusts the determining level of the slicer 203 according to a compensation signal CY of a baseline corrector 204, so as to determine the state value corresponding to the input signal EY After that, an error SY before and after the determining process is output. In addition, the baseline corrector 204 calculates the slicer error SY statistically, and then outputs the compensation signal CY accordingly.
In the method of FIG. 2, the signal EY output from the equalizer 202 and the signal SY output from the slicer all have a higher number of bits, so the compensation is quite precise. However, a front end signal BY entering the ADC 201 is not compensated, which may cause the saturation of the ADC 201. In order to avoid the saturation, an auto gain controller is used to adjust the gain of the front end signal BY that enters the ADC 201, and thus, the swing range of the signal BY becomes smaller, and the SNR is reduced.
In a communication system, whether or not the baseline wandering occurs or how severe the baseline wandering will be cannot be estimated, so during circuit designs, a designer has to consider the worst situation, i.e., killer pattern in the University of New Hampshire (UNH) certification. However, in order to successfully challenge the killer pattern, the processing capability directed to normal situations has to be designed excessively. For example, as for the circuits of FIGS. 1 and 2, the circuit of FIG. 1 uses the DAC and ADC with limited precision to adjust the DC bias of the signals, such that the signal swing range falls into the input range of the ADC to prevent the ADC saturation, and thus the signals with relatively small baseline wandering cannot be compensated precisely; in another aspect, in the circuit shown in FIG. 2, in order to prevent the saturation of the ADC, the front end signal entering the ADC is reduced, so the SNR is lowered. The two circuits are designed for special situations, but neglect the precision compensation in most normal situations.